Early DRAMs used storage cells each consisting of three transistors and were manufactured using P type channel metal-oxide-semiconductor (PMOS) technology. Later, a DRAM storage cell structure consisting of one transistor and one capacitor was developed. The gate of the transistor is controlled by a word line signal, and data, represented by the logic level of a capacitor voltage, is written into or read out of the capacitor through a bit line.
As the semiconductor memory device becomes more highly integrated, the area occupied by a capacitor of a DRAM storage cell typically shrinks. Thus, the capacitance of the capacitor is reduced owing to its smaller electrode surface area. However, a relatively large capacitance is required to achieve a high signal-to-noise ration in reading the memory cell and to reduce soft errors (due to alpha particle interference). Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance, thereby achieving both high cell integration and reliable operation.
When DRAM cells are scaled down while maintaining the cell capacitance, three-dimensional cell structures, such as trench capacitors, are widely developed. One of advantages of the trench capacitor cell is its large capacitance and planar topography. One of the prior arts in accordance with the trench capacitor can be seen "A 0.6 .mu.m.sup.2 256 Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), L. Nesbit et al., 1993, IEEE, IEDM 93-627". A unique feature of this cell is a self-aligned buried strap that forms at the intersection of the storage trench and the junction of the array device. However, it is difficult to make deep trenches with a high aspect ratio for high density DRAMs.
An example of a conventional deep trench capacitor is depicted in FIG. 1A to FIG. 1C. Referring to FIG. A, that shows a dielectric layer 102 is formed on a semiconductor substrate 101, and a trench region 100 is formed by dry etching down. After the trench is etched, the N-type capacitor plate 103 is formed by outdiffusing arsenic or phosphoric from the lower portion of the trench. An oxidized nitride (NO) storage node dielectric 104 is formed in the storage trench, followed by the deposition and controlled recess of a first trench fill of n+ polysilicon 105. See FIG. 1B, a collar oxide 106 is formed using conventional CVD process. The depth of buried strap is defined by a controlled etchback of a second polysilicon trench fill 107 and the removal of the exposed collar oxide. A third polysilicon film 108, which contacts the silicon substrate along the exposed trench sidewall, is deposited and recessed below the silicon substrate surface.